Display device driving apparatus and display device using the same

ABSTRACT

In a drive unit for use with a matrix type display, a buffer circuit of the power supply circuit of the drive unit has an high-voltage first output circuit and a low-voltage second output circuit for generating the same output voltage under a normal operating condition, wherein the high-voltage output circuit has enhanced capability of providing output current to bring up the output voltage and the low-voltage output circuit has enhanced capability of providing output current to bring down the output voltage. A voltage detected at a node connected to the output end of the buffer circuit is compared with a bias voltage. Based on the comparison, the outputs of the first and second output circuits are switched over from one to the other as it is supplied to the display.

FIELD OF THE INVENTION

This invention relates to a display drive unit suitable for a matrixtype liquid crystal display (LCD) for example, and to a displayutilizing such display drive unit.

BACKGROUND OF THE INVENTION

Matrix type LCDs having multiple rows of striping electrodes (referredto as scanning electrodes or common electrodes) and multiple columns ofelectrodes (referred to signaling electrodes or segment electrodes)arranged perpendicular to the scanning electrodes have been widely usedas means for displaying information in dot presentation.

A picture is displayed on such an LCD display by applying a scanningvoltage to the respective scanning electrodes in turn and simultaneouslyapplying a signaling voltage to the multiple signaling electrodes.Liquid crystal elements (LCES) are formed at the intersections of thescanning electrodes and the signaling electrodes one for eachintersection.

Each of the LCEs is controlled to have a specific transparencydetermined by an applied effective voltage for a predetermined period oftime (one frame period) required to scan all the scanning electrodesonce. This scanning provides a desired picture on the display for eachframe period.

Referring to FIG. 8, there is shown a circuit arrangement of aconventional display drive for an LCD. The display drive generates firstthrough sixth output voltages V0, V1, V2, V3, V4, and V5, respectively,to be supplied to the LCD. It should be understood that voltagesrepresent potentials with respect to the ground potential unlessotherwise stated. The LCD includes a display panel, a scanning drivecircuit for sequentially scanning the scanning electrodes, and asignaling drive circuit for applying a signal voltage to the respectivesignaling electrodes in synchronism with the scanning.

A step-up circuit CHP comprises of a charge pump circuit, which isadapted to receive a supply voltage Vcc from a battery and a clocksignal clk and step up the voltage Vcc to a step-up supply voltage Vdd.

The supply voltage Vdd is supplied to a voltage amplifier A1 togetherwith a reference voltage Vref to obtain a first bias voltage V0 r byamplifying the reference voltage Vref by a predetermined factor. Thefirst bias voltage V0 r is then divided by resistors R0-R4 to obtainsecond through fifth bias voltages V1 r-V4 r, respectively.

The first through the fifth bias voltages V0 r-V4 r are respectivelyinput to a first through a fifth buffer circuits B0-B4 operating at thesupply voltage Vdd, each of which outputs the same voltage V0-V4 as therespective input voltage V0 r-V4 r. The sixth voltage V5 has the groundpotential.

Of these output voltages V0-V5, the first, second, fifth, and sixthoutput voltages V0, V1, V4, and V5 are supplied to the scanning drivecircuit of the LCD. The first, third, fourth, and sixth output voltagesV0, V2, V3, and V5 are supplied to the signaling drive circuit. Theseoutput voltages are selected and used in synchronism with an alternationsignal FR of the LCD. In what follows the alternation signal FR will bedescribed for one frame period.

FIG. 9 illustrates typical waveforms of drive voltages applied to aparticular set of scanning electrode COMj and signaling electrode SEGkof an LCD having n scanning electrodes and m signaling electrodes.

In odd numbered frames (for which FR being high (H)), scanningelectrodes COM1-COMn are scanned to sequentially select one scanningelectrode, COMj say, at a time. The selected scanning electrode COMMj issupplied with the first output voltage V0. The rest of the scanningelectrodes COM1-COMn (excluding COMj) are supplied with the fifth outputvoltage V4. On the other hand, the signaling electrodes SEG1-SEGm aresupplied with either the fourth voltage V3 or the sixth voltage V5 inaccord with the display signal associated with the selected scanningelectrode selected.

Similarly, in the even numbered frames (for which FR being low (L)), thescanning electrodes COM1-COMn are scanned to sequentially select onescanning electrode at a time. The selected electrode COMj, say, issupplied with the sixth voltage V5. The rest of the scanning electrodesCOM1-COMn excluding COMj are supplied with the second output voltage V1.On the other hand, signaling electrodes SEG1-SEGm are supplied witheither the first output voltage V0 or the third output voltage V2 inaccord with the display signal associated with the selected scanningelectrode selected.

In this way, under the alternation control of the display elements, apicture defined by the display signal is displayed on the LCD.

Each of the display elements of the LCD functions as a capacitiveelement. As a consequence, when the voltage of a signaling electrodechanges, the voltage of the scanning electrode associated with thesignaling electrode varies, exhibiting a noise voltage. This voltagevariation causes crosstalks, resulting in degradation of the quality ofthe displayable picture displayed.

As a measure against such voltage variations, a power supply unit foruse with an LCD drive is disclosed in a reference WO00/41028 (Reference1). This unit comprises: two voltage-follower type differentialamplifiers each receiving a pair of a first and a second voltages NV andPV, respectively; an N-type transistor output circuit driven by one ofthe two differential amplifiers; and a P-type transistor output circuitdriven by the other one of the differential amplifiers.

This power supply unit is also provided with separate charging anddischarging operational amplifiers for driving liquid crystal displayelements. JPA H9-292596 (Reference 2) and JPA H9-203885 (Reference 3)disclose a power supply circuit for use in an LCD drive adapted toswitch between two operational amplifiers at the timing of charging anddischarging by means of a switching circuit and a timing circuitgenerating a timing pulse for the switching.

However, in the power supply unit of reference 1 the pair of voltages NVand PV to be supplied to the two differential amplifiers have differentmagnitudes, that is, there is an offset between them, so that the powersupply unit has a dead band in which both of the differential amplifiersbecome inoperable. It is noted that the voltage at the output node ofthe output circuit is detected. Hence, the voltage variation (or noise)that has taken place on the display electrode is greatly damped by aselector (voltage selection switch) of the drive circuit before it isdetected at the output node of the output circuit. For this reason, thevoltage variation (noise) on the display electrode cannot be detectedaccurately.

In the output circuits of references 2 and 3, charging and dischargingoperational amplifiers are switched by a timing signal. Thus, additionalcircuit means for generating the timing signal is necessary. Further,these drive units cannot control the switching to suppress the voltagevariation.

It is, therefore, an object of the present invention to provide adisplay drive unit suitable for driving, for example, a matrix type LCD,the drive unit adapted to detect the voltage near the display panel andincluding a first output circuit having enhanced capability of providingoutput current to bring up its output voltage and a second outputcircuit having enhanced capability of providing output current to bringdown its output voltage and capable of switching between the two outputcircuits without any dead band, thereby reducing crosstalks in, andhence improving the picture quality of, the display panel.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, there is provided adrive unit for driving a display having display elements arranged in amatrix (the unit hereinafter referred to as display drive unit and thedisplay elements referred to as matrix type display elements), thedisplay drive unit comprising:

a resistive voltage-dividing circuit for dividing a display referencevoltage into multiple bias voltages;

multiple buffer circuits for respectively converting the multiple biasvoltages into output voltages through impedance conversion of the biasvoltages;

a scanning drive circuit adapted to select from the output voltages ofthe multiple buffer circuits a voltage to be applied to the scanningelectrodes of the matrix type display elements and apply the selectedvoltage to the scanning electrodes; and

a signaling drive circuit adapted to select from the output voltages ofthe multiple buffer circuits a voltage to be applied to the signalingelectrodes of the matrix type display elements and apply the selectedvoltage to the signaling electrodes, wherein at least one of themultiple buffer circuits includes:

a first output circuit receiving the bias voltage supplied to the buffercircuit and the output voltage of the buffer circuit, and havingenhanced drive capability of providing output current to bring up theoutput voltage;

a first output switch for allowing the first output circuit to outputits power;

a second output circuit receiving the bias voltage supplied to thebuffer circuit and the output voltage of the buffer circuit, and havingenhanced drive capability of providing output current for bringing downthe output voltage;

a second output switch for allowing the second output circuit to outputits power; and

a voltage comparator for comparing the bias voltage supplied to thebuffer circuit with the voltage detected at a node connected to theoutput end of the buffer circuit (the node will be referred to asdetection node and the voltage referred to as detection voltage), thevoltage comparator adapted to switch between the first and second outputswitches in accord with the comparison.

The voltage comparator preferably has a hysteresis characteristic. Thevoltage range of the hysteresis may be set not to include the biasvoltage.

In accordance with another aspect of the invention, there is provided adisplay drive unit for driving a display having matrix type displayelements, the display drive unit comprising:

a resistive voltage-dividing circuit for dividing a display referencevoltage into multiple bias voltages;

multiple buffer circuits for respectively converting the multiple biasvoltages into output voltages through impedance conversion of the biasvoltages;

a scanning drive circuit adapted to select a voltage to be applied tothe scanning electrodes of the matrix type display elements from theoutput voltages of the multiple buffer circuits and apply the selectedvoltage to the scanning electrodes; and

a signaling drive circuit adapted to select from the output voltages ofthe multiple buffer circuits a voltage to be applied to the signalingelectrodes of the matrix type display elements and apply the selectedvoltage to the signaling electrodes, wherein

one of the multiple buffer circuits (referred to as high-voltage buffercircuit) includes:

a first output circuit receiving the bias voltage supplied to thehigh-voltage buffer circuit and the output voltage of the high-voltagebuffer circuit, and having enhanced drive capability of providing outputcurrent to bring up the output voltage;

a first output switch for allowing the first output circuit to outputits power;

a second output circuit receiving the bias voltage supplied to thehigh-voltage buffer circuit and the output voltage of the high-voltagebuffer circuit, and having enhanced drive capability of providing outputcurrent for bringing down the output voltage;

a second output switch for allowing the second output circuit to outputits power; and

a first voltage comparator for comparing the bias voltage supplied tothe high-voltage buffer circuit with the voltage obtained by detectingthe voltage applied to the display elements not in display mode (thevoltage referred to as detection voltage), the voltage comparatoradapted to switch between the first and second output switches in accordwith the comparison. Further, another one of the multiple buffercircuits (the buffer circuit hereinafter referred to as low-voltagebuffer circuit) includes;

a third output circuit receiving a bias voltage lower than the biasvoltage for the high-voltage buffer circuit along with the outputvoltage of the low-voltage buffer circuit, and having enhance drivecapability of providing output current to bring up the output voltage;

a third output switch for allowing the third output circuit to outputits power;

a fourth output circuit receiving the bias voltage supplied to thelow-voltage buffer circuit and the output voltage of the low-voltagebuffer circuit, and having enhance drive capability of providing outputcurrent to bring down the output voltage;

a fourth output switch for allowing the fourth output circuit to outputits power; and

a second voltage comparator for comparing the bias voltage supplied tothe low-voltage buffer circuit with the detection voltage, the voltagecomparator adapted to switch between the third and fourth outputswitches in accord with the comparison.

The detection voltage is taken at a node (referred to as detection node)connected to the output end of the high-voltage buffer circuit via afirst selection switch and to the output end of the low-voltage buffercircuit via the second selection switch; and either one of the first andsecond selection switches is selected by an alternation signal.

The first and second voltage comparators preferably have hysteresischaracteristics.

The first voltage comparator may have a hysteresis in a region where thedetection voltage is slightly above the bias voltage supplied to thehigh-voltage buffer circuit, while the second voltage comparator mayhave a hysteresis in a region where the detection voltage is slightlybelow the bias voltage supplied to the low-voltage buffer circuit.

A display of the invention comprises a matrix type display panel drivenby any one of the display drive units as described above.

In an inventive display drive unit suitable for driving a display suchas a matrix type LCD, at least one of multiple buffer circuits includesa parallel connection of: a first output circuit having enhanced drivecapability of providing output current to bring up the output voltage ofthe buffer circuit and connected to a first output switch for allowingthe first output circuit to output its power; and a second outputcircuit having enhanced drive capability of providing output current forbringing down the output voltage and connected to a second output switchfor allowing the second output circuit to output its power, wherein thefirst and the second output circuits are supplied with the same biasvoltage. Thus, no dead band arises in the operation of the first and thesecond output circuits, so that the buffer circuit promptly recovers itspredetermined output voltage.

The display drive unit of the invention is provided with a voltagecomparator for comparing the bias voltage supplied to the buffer circuitwith the detection voltage detected at a node connected to the outputend of the buffer circuit (or the detection voltage indicative of thevoltage applied to a relevant display element not in display mode), andadapted to switch between the first and second output switches based onthe comparison, so that the noise contained in the detection voltage isabsorbed. As a result, since the output circuit not providing outputcurrent is also in a predetermined operational mode, the buffer circuitcan provide appropriate output voltage immediately after the first andsecond output switches are switched from one to the other.

The drive unit of the invention is responsive to a small noise and canpromptly absorb it, since the detection voltage is taken at a detectionnode close to the source of the noise. Thus, crosstalks in the displaypanel are reduced, thereby improving the picture quality of the display.

Comparison of the output voltages of the inventive output circuits andswitching of the outputs thereof can be performed in a stable manner.This can be done by setting up a hysteresis in the voltage comparator ofthe output circuits, or, in the case where the output circuits include afirst and a second voltage comparators, by setting up a first hysteresisin the first voltage comparator in a region where the detection voltageis slightly above the bias voltage of the high-voltage buffer circuittherefor, and a second hysteresis in the second voltage comparator in aregion where the detection voltage is slightly below the bias voltage ofthe low-voltage buffer circuit.

It is noted that a common detection voltage can be used for thehigh-voltage and low-voltage buffer circuits, so that a single feedbackloop can be used for two different voltage comparators. In the inventivedisplay, noise due to crosstalks is reduced, which improves the picturequality of the display.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit arrangement of an LCD in accordance with oneembodiment of the invention.

FIG. 2 shows a circuit arrangement of the power supply circuit shown inFIG. 1.

FIG. 3.A shows a circuit arrangement of a buffer circuit of the powersupply circuit.

FIG. 3.B is a circuit arrangement of another buffer circuit of the powersupply circuit.

FIG. 3.C is a circuit arrangement of a still another buffer circuit ofthe power supply circuit.

FIG. 3.D shows a circuit arrangement of a further buffer circuit of thepower supply circuit.

FIG. 3.E is a circuit arrangement of a still further buffer circuit ofthe power supply circuit.

FIG. 4.A is a graphical representation of an operational characteristicof a first voltage comparator constituting the power supply circuit.

FIG. 4.B is a graphical representation of an operational characteristicof a second voltage comparator constituting the power supply circuit.

FIG. 5 shows a circuit arrangement of a signaling drive circuit.

FIG. 6 shows a circuit arrangement of a scanning drive circuit

FIG. 7.A shows a circuit diagram of an exemplary analog switch.

FIG. 7.B shows a circuit diagram of another exemplary analog switch.

FIG. 8 shows a circuit arrangement of a conventional power supply unit.

FIG. 9 shows waveforms of drive signals for use with a liquid crystaldisplay panel.

BEST MODE FOR CARRYING OUT THE INVENTION

A display drive unit of the invention and a display utilizing thedisplay drive unit will now be described in detail with reference toaccompanying drawings.

Referring to FIG. 1, there is shown a circuit arrangement of an LCD inaccordance with one embodiment of the invention. The LCD has a matrixdisplay 10, a drive circuit for scanning (scanning drive circuit) 20, adrive circuit for signaling (signaling drive circuit) 30, a power supplycircuit 40, and a control circuit 50. It should be understood that anorganic EL display utilizing organic EL elements could be used in placeof the LCD.

Referring to FIG. 2, there is shown a circuit diagram of the powersupply circuit 40. FIGS. 3.A-3.E show circuit arrangements of buffercircuits of the power supply circuit. FIGS. 4.A and 4.B show operationalcharacteristics of voltage comparators of the power supply circuit.FIGS. 7.A and 7.B show circuit diagrams of exemplary analog switches.

As shown in FIG. 1, the display 10 is provided with multiple signalingelectrodes (or segment electrodes) X (X1-Xm) and multiple scanningelectrodes (or common electrodes) Y (Y1-Yn), the two types of electrodesformed on two facing substrates such that they are perpendicular to eachother. The signal and scanning electrodes are respectively formed ofabout several hundreds of electrodes. Inserted between the respectivesignaling electrodes X and scanning electrodes Y are liquid crystaldisplay elements of a simple matrix display for example, the LCDelements forming display elements at the respective intersections of theelectrodes.

The power supply circuit 40 generates a multiplicity of differentvoltages (six voltages V0-V5 in this example) necessary for alternationcontrol of the display. These voltages are supplied to either thescanning drive circuit 20 or the signaling drive circuit 30. Thevoltages V0-V5 are fixed at predetermined levels, respectively, whichbecome smaller (or larger) in magnitude in the order mentioned. Themultiplicity of the voltages can be more than six, or less ifalternation control is not needed.

The control circuit 50 generates display data D, clocks, and differentkinds of control signals, which are supplied to the scanning drivecircuit 20 and the signaling drive circuit 30. The display data Dinclude data for controlling signals (e.g. PWM data) to be supplied tothe signaling electrodes X1-Xm. The display data D is supplied to thesignaling drive circuit 30. The tone of the display 10 is controlledbased on the display data D.

A data shifting clock CK, supplied to the signaling drive circuit, isfor shifting the display data D. A scanning clock LP serves as ascanning signal for scanning the scanning electrodes Y when it issupplied to the scanning drive circuit 20, and serves as a latch signalfor latching the display data D for one line of display data D whensupplied to the signaling drive circuit 30. An alternation signal FR isan inverting/non-inverting signal (having a high (H) or a low (L) level)for performing alternation driving of the LCD. When alternation drivingis not needed, the alternation signal FR is not required.

A start signal ST is supplied to the scanning drive circuit 20 forstarting scanning.

The scanning drive circuit 20 thus receives a start signal ST, ascanning clock LP, and alternation signal FR. Then the scanning drivecircuit 20 generates a predetermined scanning voltage to be supplied tothe scanning electrodes Y1-Yn in turn to scans these electrodes Y1-Yn ata predetermined clock interval.

Details of the power supply circuit 40 shown in FIG. 2 will now bedescribed. A power supply voltage Vcc input from a battery for exampleand a clock clk are supplied to a step-up circuit CHP, which outputs astep-up power supply voltage Vdd. The step-up circuit CHP comprises of,for example, a charge pump circuit, and has at the output end thereof asmoothing capacitor for smoothing the power supply voltage Vdd.

The power supply voltage Vdd is supplied to a voltage amplifier A1,which amplifies a reference voltage Vref by a predetermined factor toform a display reference voltage. This display reference voltage servesas a first bias voltage (first reference voltage) V0 r. The displayreference voltage is divided by resistors R0-R4 into a first biasvoltage (first reference voltage) V0 r, a second bias voltage (secondreference voltage) V1 r, a third bias voltage (third reference voltage)V2 r, a fourth bias voltage (fourth reference voltage) V3 r, and a fifthbias voltage (fifth reference voltage) V4 r.

The first through fifth reference voltages V0 r-V4 r are respectivelyinput to a first through a fifth buffer circuits B0-B4, whichrespectively output a first through a fifth output voltages V0-V4, eachhaving the same level as the corresponding reference voltage V0 r-V4 r.In the example shown herein, the power supply voltage Vdd higher thanthe output voltages V0-V4 of the respective buffer circuits is used todrive the buffer circuits B0-B4. Alternatively, the output voltagesV0-V3 may be used for the same purpose. The sixth voltage V5 equals theground potential.

Of these first through sixth voltages V0-V5, the first, second, fifth,and sixth output voltages, V0, V1, V4, and V5, respectively, aresupplied to the scanning drive circuit 20 of the LCD. On the other hand,the first, third and fourth output voltages V0, V2, and V3,respectively, and the sixth voltage V5 are supplied to the signalingdrive circuit 30 of the LCD. These voltages are selected in synchronismwith the alternation signal FR of the LCD, in the manner as described inconnection with FIG. 9.

Referring to FIG. 3.A, there is shown a circuit arrangement of the firstbuffer circuit B0. The first buffer circuit B0 is provided with a P-typeMOS transistor Q0 connected between the power supply voltage Vdd and thefirst output voltage V0, and with a constant-current source I0 forflowing weak current (1 micro-ampere, for example) between the firstoutput voltage V0 and the ground. The constant-current source 10 isprovided to stabilize the operation of the buffer circuit. Otherconstant-current sources used in other buffer circuits are provided forthe same purpose.

Also, there is provided an operational amplifier OP0 receiving the firstreference voltage V0 r and the first output voltage V0 to output acontrol signal to the P-type MOS transistor Q0. In first buffer circuitB0, current flows through the P-type MOS transistor Q0, wherein theP-type MOS transistor Q0 is controlled such that the first outputvoltage V0 is equilibrated to the first reference voltage V0 r. Sincecurrent flows from the power supply voltage Vdd via the P-type MOStransistor Q0, the first buffer circuit B0 serves as an output circuithaving enhanced drive capability of providing output current to bring upthe first output voltage V0 if the output voltage V0 has lowered.

FIG. 3.B shows a circuit arrangement of the second buffer circuit B1.The second buffer circuit B1 has a first circuitry that includes aP-type MOS transistor Q1 p and a first output switch SW1 p connected inseries between, for example, the power supply voltage Vdd and the secondoutput voltage V1. The second buffer circuit B1 also has a secondcircuit that includes a second output switch SW1 n and an N-type MOStransistor Q1 n connected in series between the second output voltage V1and the ground. A constant-current source I1 p is provided for flowingweak current between the output end (drain) of the P-type MOS transistorQ1 p and the ground. Another constant-current source I1 n is providedfor flowing weak current between the power supply voltage Vdd and theoutput end (drain) of an N-type MOS transistor Q1 n.

There are provided an operational amplifier OP1 p receiving the secondreference voltage V1 r and the second output voltage V1 to output acontrol signal to the P-type MOS transistor Q1 p, and an operationalamplifier OP1 n receiving the second reference voltage V1 r and thesecond output voltage V1 to output a control signal to the N-type MOStransistor Q1 n. In the second buffer circuit B1, current flows throughthe P-type MOS transistor Q1 p when the first output switch SW1 p isturned on, while current flows through the N-type MOS transistor Q1 nwhen the second output switch SW1 n is turned on. In either case, theP-type and the N-type MOS transistors Q1 p and Q1 n, respectively, arecontrolled to equilibrate the second output voltage V1 with the secondreference voltage V1 r.

The circuitry that includes the P-type MOS transistor Q1 p and theoperational amplifier OP1 p constitutes a first output circuit B1 phaving enhanced drive capability of providing output current to bring upthe second output voltage V1, while the circuitry that includes theN-type MOS transistor Q1 n and the operational amplifier OP1 nconstitutes a second output circuit B in having enhanced drivecapability of providing output current to bring down the second outputvoltage V1.

In this way, the second buffer circuit B1 has the first circuitry havingthe first output circuit B1 p and the first output switch SW1 p toacquire enhanced drive capability of providing output power to bring upits output voltage and the second circuitry having the second outputcircuit B1 n and the second output switch SW1 n to acquire enhanceddrive capability of providing output power to bring down its outputvoltage, with the first and second output circuits connected together inparallel and receiving the same reference voltage V1 r. Thus, no deadband will arise in the operation of the first and second output circuitsB1 p and B1 n, respectively.

It is noted that the first output switch SW1 p and the second outputswitch SW1 n are controlled by a first voltage comparator CP1 as shownin FIG. 2 such that the two switches SW1 p and SW1 n are exclusivelyturned on and off in accordance with the output of the first comparatorCP1. The first voltage comparator CP1 has a hysteresis characteristic.For example, when the second output voltage V1 is raised from a lowerlevel as controlled by the first voltage comparator CP1, the firstoutput switch SW1 p is turned on. On the other hand, when the secondoutput voltage V1 is lowered from a higher level, the second outputswitch SW1 n is turned on.

The first voltage comparator CP1 may be provided in the second buffercircuit B1 as a part thereof.

Since the first output voltage V0 has a higher voltage than the secondoutput voltage V1, the first output voltage V0 may be utilized, in placeof the power supply voltage Vdd, as the operational power source for thesecond buffer circuit B1 and the first voltage comparator CP1.Similarly, instead of the power supply voltage Vdd, an output voltage ofone buffer circuit may be utilized as the operational power source ofanother buffer circuit if the former buffer circuit has a higher outputvoltage than the latter.

FIG. 3.C shows a circuit arrangement of the third buffer circuit B2. Thethird buffer circuit B2 has an N-type MOS transistor Q2 connectedbetween the third output voltage V2 and the ground, and aconstant-current source I2 for flowing weak current between the powersupply voltage Vdd and the third output voltage V2. The third buffercircuit B2 also has an operational amplifier OP2 for generating andsupplying a control signal to the N-type MOS transistor Q2.

In the third buffer circuit B2, current flows through an N-type MOStransistor Q2, wherein the n-type MOS transistor Q2 is controlled insuch a way that the third output voltage V2 is equilibrated to the thirdreference voltage V2 r. Since current flows from the third outputvoltage V2 into the third buffer circuit B2, allowing the current toflow through the N-type MOS transistor Q2, the third buffer circuit B2serves as an output circuit having enhance drive capability of providingoutput current to bring down third output voltage V2.

FIG. 3.D shows a circuit arrangement of the fourth buffer circuit B3.The fourth buffer circuit B3 is similar in structure to the first buffercircuit B0, receiving as its reference voltage the fourth output voltageV3 r and providing the fourth output voltage V3.

FIG. 3.E shows a circuit arrangement of the fifth buffer circuit B4. Thefifth buffer circuit B4 is similar in structure to the second buffercircuit B1 of FIG. 3.B, receiving the fifth reference voltage V4 r asits reference voltage and providing the fifth output voltage V4. As aresult, the circuitry that includes the P-type MOS transistor Q4 p andthe operational amplifier OP4 p constitutes a third output circuit B4 phaving enhanced drive capability of providing drive current to bring upthe fifth output voltage V4. The circuitry that includes the N-type MOStransistor Q4 n and the operational amplifier OP4 n constitutes a fourthoutput circuit B4 n having enhanced drive capability of providing drivecurrent to bring down the fifth output voltage V4. A constant-currentsource I4 p is provided for flowing weak current between the output end(drain) of the P-type MOS transistor Q4 p and the ground, and aconstant-current source I4 n for flowing weak current between the powersupply voltage Vdd and the output end (drain) of an N-type MOStransistor Q4 n.

It is noted that the third output switch SW4 p and the fourth outputswitch SW4 n are controlled by the second voltage comparator CP4 suchthat the two output switches SW4 p and SW4 n are exclusively turned onand off in accord with the output of the comparator CP4. The secondvoltage comparator CP4 has a hysteresis characteristic. For example,when the fifth output voltage V4 is raised from a lower level ascontrolled by the second voltage comparator CP4, the third output switchSW4 p is turned on. On the other hand when the fifth output voltage V4is lowered from a higher level, the fourth output switch SW4 n is turnedon.

The second voltage comparator CP4 may be provided in the fifth buffercircuit B4 as a part thereof.

The first voltage comparator CP1 is supplied with the second referencevoltage V1 r and a detection voltage Vdet1·4 that is supplied to thedisplay elements not in display mode, and compares the magnitudes ofthese voltages. The second voltage comparator CP4 is supplied with thefifth reference voltage V4 r and the detection voltage Vdet1·4, andcompares these voltages.

Incidentally, in the scanning drive circuit 20, either the second outputvoltage V1 or the fifth output voltage V4 is selected by a commonvoltage selection switch (analog switch) in accordance with the level (Hor L) of the alternation signal FR. The selected voltage is supplied tothe respective scanning electrodes Y1-Yn via a non-selective scanningswitch. The detection voltage Vdet1·4 refers to the voltage that isselected by the analog switch for application to the scanning electrodesY1-Yn. That is, the detection voltage Vdet1·4 is the voltage applied tothe display elements not in display mode (either the second outputvoltage V1 or the fifth output voltage V4.) Therefore, the detectionvoltage Vdet1·4 is close to the voltage actually applied to the scanningelectrodes Y1-Yn. For this reason, the detection voltage Vdet1·4reflects the voltage variation (noise) on the scanning electrodes Y1-Ynmore accurately without being much influenced by the voltage drops(attenuation) caused by analog switches. A node providing the detectionvoltage Vdet1·4 will be referred to as detection node.

FIG. 4.A shows the operational characteristic of the first voltagecomparator CP1 as a function of the detection voltage Vdet1·4. In theexample shown in FIG. 4.A, the output of the first comparator CP1remains low (L) while the detection voltage Vdet1·4 is lower than alevel which is slightly (3 mV for example) larger than the secondreference voltage V1 r. As a consequence, the first output switch SW1 pis normally turned on, thereby causing the first output circuit B1 p tooutput the second output voltage V1. As a consequence, when thedetection voltage Vdet1·4 changes from the fifth output voltage V4 tothe second output voltage V1, current will flow out of the first outputcircuit B1 p without any time lag due to switching.

When the detection voltage Vdet1·4 exceeds a level higher than thesecond reference voltage V1 r by a predetermined voltage (20 mV forexample), the output voltage of the first voltage comparator CP1 ispulled up to H level, thereby turning on the second output switch SW1 n.This causes current to flow into the second output circuit B1n, whichabsorbs noise of positive polarity.

In order to allow smooth switching of the first and second outputswitches SW1 p and SW1 n, respectively, the first voltage comparator CP1preferably has a hysteresis of about 20 mV in width. The hysteresis maybe set up, in a region slightly above the second reference voltage V1 r,to have a predetermined width, ranging from V1 r+α (e.g. α=3 mV) to V1r+β (e.g. β=20 mV).

FIG. 4.B shows an operational characteristic of the second voltagecomparator CP4 as a function of the detection voltage Vdet1·4. Thisdetection voltage Vdet1·4 is the same as used for the first voltagecomparator CP1. The output voltage of the second voltage comparator CP4remains high (H) while the detection voltage Vdet1·4 is higher than alevel which is slightly lower than the fifth reference voltage V4 r, asshown in FIG. 4.B. As a consequence, the fourth output switch SW4 n isnormally turned on, thereby causing the fourth output circuit B4 n tooutput the fifth output voltage V4. As a consequence, when the detectionvoltage Vdet1·4 changes from the second output voltage V1 to the fifthoutput voltage V4, current will flow into the fourth output circuit B4 nwithout any time lag due to switching.

When the detection voltage Vdet1·4 is lower than a level below the fifthreference voltage V4 r by a predetermined voltage (20 mV for example),the output level of the second voltage comparator CP4 is pulled down toL level, thereby turning on the third output switch SW4 p. This causescurrent to flow out of the third output circuit B4 p, absorbing noisehaving a negative polarity.

In order to allow smooth switching of the third and fourth outputswitches SW4 p and SW4 n, respectively, the second voltage comparatorCP4 preferably has a hysteresis. The hysteresis may be set up, in aregion slightly below the fifth reference voltage V4 r, to have apredetermined width.

FIG. 5 shows a circuit arrangement of the signaling drive circuit 30. Asshown in FIG. 5, display data D is supplied to a shift register 61 insequence and in synchronism with a data shifting clock CK in a datashifting operation. Display date D for one line (D1-Dm) is latched in alatch circuit 62 in response to a scanning clock LP.

Each of the signaling electrodes X1-Xm is provided with a pair of one“latch data” switch Swx1 a-SWxma that is turned on when data to belatched exist and one “null data” switch SWx1 b-SWxmb that is turned offwhen no such data exists. Either the switch SWx1 a-SWxma or the switchSWx1 b-SWxmb is turned on according to the display data D (D1-Dm)latched.

The first output voltage V0 is supplied to the switches SWx1 a-SWxma viaa segment voltage selection switch SWs0, or the sixth voltage V5 issupplied to the switches SWx1 a-SWxma via a segment voltage selectionswitch SWs5. The third output voltage V2 is supplied to the null-dataswitches SWx1 b-SWxmb via a segment voltage selection switch SWs2, orthe fourth output voltage V3 is supplied to the null-data switches SWx1b-SWxmb via a segment voltage selection switch SWs3.

The segment voltage selection switches SWs5 and SWs3 are selected forodd numbered frames when the alternation signal FR is high (H). Thesegment voltage selection switches SWs0 and SWs2 are selected for evennumbered frames when the alternation signal FR is low (L). Thus, as isthe case with the scanning electrode COMj shown in FIG. 9, odd numberedframes are supplied with either the sixth voltage V5 or the fourthoutput voltage V3, in accord with the relevant display data, while evennumbered frames are supplied with either the first output voltage V0 orthe third output voltage V2.

FIG. 6 shows a circuit arrangement of the scanning drive circuit 20. Asshown in FIG. 6, the first output voltage V0 is applied to selectionscanning switches SWy1 a-SWyna via a common voltage selection switchSWc0, and the sixth voltage V5 is applied to the selection scanningswitches SWy1 a-SWyna via a common voltage selection switch SWc5. Thesecond output voltage V1 is supplied to non-selection scanning switchSWy1 b-SWynb via a common voltage selection switch SWc1, and the fifthoutput voltage V4 is supplied to the non-selection scanning switch SWy1b-SWynb via a common voltage selection switch SWc4.

The selection switches SWc0 and SWc4 are selected for odd numberedframes when the alternation signal FR is high (H). On the other hand,the selection switches SWc5 and SWc1 are selected for the even numberedframes when the alternation signal FR is low (L).

Each of the scanning electrodes Y1-Yn is provided with a pair of oneselection scanning switch SWy1 a-SWyna and one non-selection scanningswitch Swy1 b-SWynb.

Upon receipt of a scanning clock LP following a start signal ST, ascanning circuit 71 sequentially turns on the selection scanningswitches SW1 a-SWyna, one at a time.

Thus, as in the case with the scanning electrode COMj shown in FIG. 9,only one scanning electrode is selectively pulled up to the first outputvoltage V0 in the odd numbered frames, while the rest of the scanningelectrodes are supplied with the fifth output voltage V4. In the evennumbered frames, only one of the scanning electrodes is selectivelypulled up to the sixth voltage V5 and the rest of the scanningelectrodes are supplied with the second output voltage V1.

In the scanning drive circuit 20, the position (node) to which thenon-selection scanning switch SWy1 b-SWynb are connected, that is, theposition from where the second output voltage V1 or the fifth outputvoltage V4 is supplied via the common voltage selection switch SWc1 orcommon voltage selection switch SWc4, is taken to be the node where thedetection voltage Vdet1·4 is detected.

FIGS. 7.A and 7.B respectively show circuit arrangements of an analogswitch suitable for flowing bi-directional current.

This analog switch comprises a CMOS transistor 5 a consisting of aP-type MOS transistor connected in series with an N-type transistor, aninverter 5 b having an output terminal connected to one input terminalof the CMOS transistor 5 a, and a control signal line S1 that isconnected to the other input terminal of the CMOS transistor 5 a and tothe input terminal of the inverter 5 b. The analog switch shown in FIG.7.A is turned on when the control signal line S1 is at H level andturned off when the control signal line is at L level. The analog switchshown in FIG. 7.B is turned on when the control signal line S1 is at Llevel and turned off when the control signal line is at H level.

This analog switch may be used as a switch for selecting a commonvoltage selection switch SWc0-SWc5, segment voltage selection switchSWs0-SWs5, a signaling electrode, and a scanning electrode.

In the power supply circuit 40 shown in FIG. 2, the first and thirdoutput switches SW1 p and SW4 p, respectively, are P-type MOS transistorswitch circuits, while the second and fourth output switches SW1 n andSW4 n, respectively, are N-type MOS transistor switch circuits.

Referring to the accompanying drawings, operation of the inventivedisplay will now be described in detail.

The first through sixth voltages V0-V5 output from the power supplycircuit 40 are supplied to the scanning drive circuit 20 and to thesignaling drive circuits 30 as previously described. The detectionvoltage Vdet1·4 is fed back from the detection node of the scanningdrive circuit 20 to the first and second voltage comparators CP1 andCP4, respectively, of the power supply circuit 40.

Under this condition, a start signal ST, display data D, a clock CK, ascanning clock LP, and an alternation signal FR are supplied from thecontrol circuit 50 to the scanning drive circuit 20 and the signalingdrive circuit 30. As a result, the scanning electrodes Y1-Ym are scannedand the signal data D (D1-Dm) are supplied to the signaling electrodesX1-Xm to display a picture on the display 10 in accord with the displaydata D.

In this operation, it is preferable that each of the scanning electrodesand each of the signaling electrodes are supplied with predeterminedoutput voltages. However, since each of the display elements functionsas a capacitive element, the voltages of the scanning electrodes Y1-Ynfluctuate, exhibiting a noise, in response to the changes in voltage ofthe associated signaling electrodes.

Looking at the scanning of electrodes associated with the common voltageselection switches SWc1 and SWc4, a scanning electrode in the oddnumbered frames held at the first output voltage V0 at a moment willundergo a sudden change in voltage to the fifth output voltage V4 in thenext moment. On the other hand, a signaling electrode undergoes a changeto the fourth and sixth output voltages V3 and V5, respectively. As aconsequence, the voltage at the node of the common voltage selectionswitches SWc1 and SWc4 (fifth output voltage V4 in this example)connected to the scanning electrodes cannot be held at the predeterminedlevel but fluctuates. These voltage fluctuations cause crosstalks anddegrade the picture quality of the display. This is also the case withthe even numbered frames: the voltage of scanning electrodes connectedto the common voltage selection switches SWc1 and SWc4 (which is thesecond output voltage V1 in this example) cannot be held at thepredetermined level and fluctuates. Thus, crosstalks will take place,resulting in degradation of the picture quality of the display.

According to the invention, fluctuations in voltage of the scanningelectrodes, that is, fluctuations in the second and fifth outputvoltages V1 and V4, respectively are promptly suppressed to maintainthese voltages at the predetermined levels, thereby reducing resultantcrosstalks.

Exemplary arrangements for the reduction of the fluctuations have beendescribed above. Particularly, the detection voltage Vdet1·4 to becompared with reference voltages is detected at a node as close aspossible to the scanning electrodes Y1-Yn. Specifically, the detectionvoltage is taken at a node of the common voltage selection switches SWc1and SWc4 connected to the scanning electrodes. It is noted that thisdetection voltage Vdet1·4 is fed back to the first and second voltagecomparators CP1 and CP4, respectively.

Accordingly, unlike the prior art power supply unit as disclosed in thereference 1, voltage fluctuations can be detected without beingattenuated by the common voltage selection switches SWc1 and SWc4,thereby allowing more accurate detection of the actual voltage. Thus,the voltage comparators CP1 and CP4 can promptly respond to a smallnoise and allows the display drive unit to provide the output voltagesin a stable manner.

The buffer circuit B1 is a high-voltage buffer circuit that includes thefirst voltage comparator CP1 for comparing the reference voltage V1 rwith the detection voltage Vdet1·4 detected at a detection nodeconnected to the output end of the buffer circuit B1. The first voltagecomparator CP1 is configured to have a hysteresis in a range where thedetection voltage Vdet1·4 is slightly higher than the reference voltageV1 r of the buffer circuit B1. Thus, if the scanning electrode held atthe sixth voltage V5 at a moment undergoes a sudden change in voltage tothe second output voltage V1 in the next moment, switching of the firstand second output switches SW1 p and SW1 n, respectively, does not takeplace, thereby allowing the power supply unit to promptly respond to thechange.

In the same manner, the low-voltage buffer circuit B4 includes thesecond voltage comparator CP4 for comparing the reference voltage V4 rwith the detection voltage Vdet1·4 detected at a detection nodeconnected to the output end of the buffer circuit B4. The second voltagecomparator CP4 is configured to have a hysteresis in a range where thedetection voltage Vdet1·4 is slightly lower than the reference voltageV4 r of the buffer circuit B4. Thus, if a scanning electrode held at thefirst voltage V0 at a moment undergoes a sudden change in voltage to thefifth output voltage V4 in the next moment, switching of the third andfourth output switches SW4 p and SW4 n, respectively, does not takeplace, thereby allowing the power supply unit to promptly respond to thechange.

Since the first output circuit B1 p and the second output circuit B1 nof the high-voltage buffer circuit B1 and the third output circuit B4 pand the fourth output circuit B4 n of the low-voltage buffer circuit B4are in operation at all times, changes in voltage on the scanningelectrodes that accompany the changes in voltage (V3→V5, V5→V3, V0→V2,and V2→V0) that has taken place on the associated signaling electrodescan be promptly suppressed.

Because the detection node for the detection voltage Vdet1·4 is taken atthe node of the common voltage selection switches SWc1 and SWc4 that isconnected to the scanning electrodes, a single feedback loop for feedingback a common detection voltage can be used for two voltage comparatorsCP1 and CP4 comparing two different voltages. Industrial Applicability

INDUSTRIAL APPLICABILITY

A display drive unit of the invention enables reduction of crosstalks ina matrix type display such as LCD and an organic EL display and improvesthe picture quality of the display.

1. A display drive unit for driving a display having matrix type displayelements, said display drive unit comprising: a resistivevoltage-dividing circuit for dividing a display reference voltage usingresistors to generate multiple bias voltages; multiple buffer circuitsfor respectively converting said multiple bias voltages into outputvoltages through impedance conversion of said bias voltages; a scanningdrive circuit adapted to select a voltage to be applied to the scanningelectrodes of said matrix type display elements from said outputvoltages of said multiple buffer circuits and apply the selected voltageto said scanning electrodes; and a signaling drive circuit adapted toselect a voltage to be applied to the signaling electrodes of saidmatrix type display elements from said output voltages of said multiplebuffer circuits and apply the selected voltage to said signalingelectrodes, wherein at least one of said buffer circuits includes: afirst output circuit receiving the bias voltage supplied to said buffercircuit and the output voltage of said buffer circuit, and havingenhanced drive capability of providing output current to bring up saidoutput voltage; a first output switch for allowing said first outputcircuit to output its voltage; a second output circuit receiving thebias voltage supplied to said buffer circuit and the output voltage ofsaid buffer circuit, and having enhanced drive capability of providingoutput current for bringing down said output voltage; a second outputswitch for allowing said second output circuit to output its voltage;and a voltage comparator for comparing the bias voltage supplied to saidbuffer circuit with the detection voltage detected at a node connectedto the output end of said buffer circuit, said voltage comparatoradapted to switch between said first and second output switches inaccord with the comparison.
 2. The display drive unit according to claim1, wherein said voltage comparator has a hysteresis characteristic. 3.The display drive unit according to claim 2, wherein said hysteresischaracteristic is set in a voltage region that does not include saidbias voltage.
 4. A display drive unit for driving a display havingmatrix type display elements, said display drive unit comprising: aresistive voltage-dividing circuit for dividing a display referencevoltage using resistors to generate multiple bias voltages; multiplebuffer circuits for respectively converting said multiple bias voltagesinto output voltages through impedance conversion of said bias voltages;a scanning drive circuit adapted to select a voltage to be applied tothe scanning electrodes of said matrix type display elements from saidoutput voltages of said multiple buffer circuits and apply the selectedvoltage to said scanning electrodes; and a signaling drive circuitadapted to select a voltage to be applied to the signaling electrodes ofsaid matrix type display elements from said output voltages of saidmultiple buffer circuits and apply the selected voltage to saidsignaling electrodes, wherein one of said multiple buffer circuitscomprises a high-voltage buffer circuit that includes: a first outputcircuit receiving the bias voltage supplied to said high-voltage buffercircuit and the output voltage of said high-voltage buffer circuit, andhaving enhanced drive capability of providing output current to bring upsaid output voltage; a first output switch for allowing said firstoutput circuit to output its voltage; a second output circuit receivingthe bias voltage supplied to said high-voltage buffer circuit and theoutput voltage of said high-voltage buffer circuit, and having enhanceddrive capability of providing output current for bringing down saidoutput voltage; a second output switch for allowing said second outputcircuit to output its voltage; and a first voltage comparator forcomparing the bias voltage supplied to said high-voltage buffer circuitwith the detection voltage in accord with the voltage applied to thedisplay elements not in display mode, said voltage comparator adapted toswitch between said first and second output switches in accord with thecomparison, and wherein another one of said multiple buffer circuitscomprises a low-voltage buffer circuit that includes; a third outputcircuit receiving a bias voltage lower than the bias voltage for thehigh-voltage buffer circuit along with the output voltage of saidlow-voltage buffer circuit, and having enhanced drive capability ofproviding output current to bring up said output voltage; a third outputswitch for allowing said third output circuit to output its voltage; afourth output circuit receiving the bias voltage supplied to saidlow-voltage buffer circuit and the output voltage of said low-voltagebuffer circuit, and having enhance drive capability of providing outputcurrent to bring down said output voltage; a fourth output switch forallowing said fourth output circuit to output its voltage; and a secondvoltage comparator for comparing the bias voltage supplied to saidlow-voltage buffer circuit with said detection voltage, said voltagecomparator adapted to switch between said third and fourth outputswitches in accord with the comparison, wherein: the detection node forsaid detection voltage is connected to the output end of thehigh-voltage buffer circuit via a first selection switch and to theoutput end of the low-voltage buffer circuit via the second selectionswitch; and either one of said first and second selection switches isselected by an alternation signal.
 5. The display drive unit accordingto claim 4, wherein said first voltage comparator and second voltagecomparator respectively have hysteresis characteristics.
 6. The displaydrive unit according to claim 5, wherein said first voltage comparatorexhibits a hysteresis in a region where said detection voltage isslightly above the bias voltage supplied to said high-voltage buffercircuit, and said second voltage comparator exhibits a hysteresis in aregion where said detection voltage is slightly below the bias voltagesupplied to said low-voltage buffer circuit.
 7. A display, comprising: adisplay drive unit according to any one of claims 1 through 6; and amatrix type display panel driven by said display drive unit.